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SM5837AF Variable-length 1H Delay Line LSI
OVERVIEW
The SM5837AF is a variable-length delay line LSI. It has 12-bit input/output signal which can be set to undergo a delay in the range of 31 to 2078 delay bits. Maximum operating frequency is 40MHz, making it ideal for use in video signal processing applications.
FEATURES
I I I I I
PINOUT
(Top view)
PARA RSTN
I I I I I
Variable-length 1H delay 12-bit input/output signal width 31 to 2078- bit delay length range 40MHz maximum operating frequency Selectable delay setting method * 11-bit parallel input * 3-line serial input TTL-compatible input/outputs Tristate outputs 4.75 to 5.25V operating voltage Molybenum-gate CMOS process Package: 44-pin QFP
DI0
DI1
DI2
DI3
DI4
DI5
36
DI6
35
44
43
42
41
40
39
38
37
DL0/SDI DL1/SICK DL2/LEN DL3 DL4 VSS1 DL5 DL6 DL7 DL8 DL9
34
DI7
NC
1 2 3 4 5 6 7 8 9 10 11
33 32 31 30 29 28 27 26 25 24 23
DI8 DI9 DI10 DI11 OE CLK VDD DO11 DO10 DO9 DO8
APPLICATIONS
I
Video signal image processing
12
13
14
15
16
17
18
19
20
21
VSS2
DL10
DO0
DO1
DO2
DO3
DO4
DO5
DO7
ORDERING INFORMATION
Device SM5837AF Package 44-pin QFP
PACKAGE DIMENSIONS
(Unit: mm)
12.80 0.30 10.00
12.80 0.30
10.00
DO8
NC
22
0 to 10
0.60 0.20 0.80 0.35 0.10
0.17 0.05
1.45
SEIKO NPC CORPORATION --1
1.75MAX
0 to 0.20
SM5837AF
BLOCK DIAGRAM
12 DI0 - 11 CLK
Variable-length 12-bit 1H Delay
12
Output Buffer
12 DO0 - 11
OE RSTN Delay Length Control
11 PARA Parallel/Serial Select 11 SDI SICK LEN DL0 - 10 SIPO 11 VDD VSS2 VSS1
PIN DESCRIPTION
Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Name DL0/SDI DL1/SICK DL2/LEN DL3 DL4 VSS1 DL5 DL6 DL7 DL8 DL9 DL10 DO0 DO1 DO2 DO3 VSS2 DO4 DO5 DO6 DO7 I/O1 Ip Ip Ip Ip Ip - Ip Ip Ip Ip Ip Ip O O O O - O O O O Function Delay length set parallel data bit DL0 (LSB) when PARA is HIGH, and SDI serial data input when PARA is LOW. Delay length set parallel data bit DL1 (bit 1) when PARA is HIGH, and SICK shift clock when PARA is LOW. Delay length set parallel data bit DL2 (bit 2) when PARA is HIGH, and LEN latch clock when PARA is LOW. Delay length set data bit 3 Delay length set data bit 4 Ground (0V) pin 1 Delay length set data bit 5 Delay length set data bit 6 Delay length set data bit 7 Delay length set data bit 8 Delay length set data bit 9 Delay length set data bit 10 Signal output data bit 0 Signal output data bit 1 Signal output data bit 2 Signal output data bit 3 Ground (0V) pin 2 Signal output data bit 4 Signal output data bit 5 Signal output data bit 6 Signal output data bit 7
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SM5837AF
Number 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Name NC DO8 DO9 DO10 DO11 VDD CLK OE DI11 DI10 DI9 DI8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 RSTN PARA NC I/O1 - O O O O - I Ip Ip Ip Ip Ip Ip Ip Ip Ip Ip Ip Ip Ip Ip Ip - No connection Signal output data bit 8 Signal output data bit 9 Signal output data bit 10 Signal output data bit 11 Supply (5V) pin Clock input Tristate output enable. Enable when HIGH, and disable when LOW. Signal input data bit 11 Signal input data bit 10 Signal input data bit 9 Signal input data bit 8 Signal input data bit 7 Signal input data bit 6 Signal input data bit 5 Signal input data bit 4 Signal input data bit 3 Signal input data bit 2 Signal input data bit 1 Signal input data bit 0 Reset pin. Normal operation when HIGH, and reset operation when LOW. Delay length setting method select. Parallel data (DL0 to DL10) when HIGH, and serial input (SDI, SICK, LEN) when LOW. No connection Function
1. Ip = input pin with built-in pull-up resistor, O = output.
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SM5837AF
SPECIFICATIONS
Absolute Maximum Ratings
VSS = VSS1 = VSS2 = 0V
Parameter Supply voltage range Input voltage range Storage temperature range Power dissipation Symbol VDD VIN Tstg PD Condition Rating -0.3 to 7.0 VSS - 0.3 to VDD + 0.3 -40 to 125 450 Unit V V C mW
Recommended Operating Conditions
VSS = 0V
Parameter Supply voltage range Operating temperature Symbol VDD Topr Condition Rating 4.75 to 5.25 -20 to 70 Unit V C
DC Characteristics
VDD = 4.75 to 5.25V, VSS = 0V, Ta = -20 to 70C unless otherwise noted.
Rating Parameter Symbol Condition min Current consumption Input voltage1, 2 IDD VIH VIL Output voltage3 Input current2 Input leakage current1, 2 Input leakage current1 Output high-impedance leakage current3 VOH VOL IIL ILH ILL IZH IZL IOH = -0.4mA IOL = 1.6mA VIN = 0V VIN = VDD VIN = 0V VOUT = VDD VOUT = 0V VDD = 5.0V, CLK frequency fC = 40MHz, OE = 0V - 2.4 - 4.0 - - - - - - typ - - - - - 10 - - - - max 85 - 0.5 - 0.4 20 1 1 5 5 mA V V V V A A A A A Unit
1. Pin CLK 2. Pins DI0 to DI11, PARA, DL0/SDI, DL1/SICK, DL2/LEN, DL3 to DL10, OE and RSTN 3. Pins DO0 to DO11
SEIKO NPC CORPORATION --4
SM5837AF
AC Characteristics
VDD = 4.75 to 5.25V, VSS = 0V, Ta = -20 to 70C unless otherwise noted.
Rating Parameter CLK clock cycle CLK clock HIGH-level pulsewidth CLK clock LOW-level pulsewidth SICK clock cycle SICK clock HIGH-level pulsewidth SICK clock LOW-level pulsewidth CLK, SICK and LEN rise time CLK, SICK and LEN fall time DI0 to DI11, DL0 to DL10 and RSTN setup time DI0 to DI11, DL0 to DL10 and RSTN hold time SDI setup time SD1 hold time SICK rising edge LEN rising edge LEN rising edge SICK rising edge CLK DO0 to D011 output delay CLK DO0 to D011 output hold time OE HIGH-level pulsewidth OE LOW-level pulsewidth OE DO0 to DO11 output enable delay OE DO0 to DO11 output disable delay Input capacitance Output capacitance Symbol tCP1 tCH1 tCL1 tCP2 tCH2 tCL2 tCR tCF tS1 tH1 tS2 tH2 tCE tEC tPD tOH tOEH tOEL tPZL tPZH tPLZ tPHZ CIN COUT f = 1MHz f = 1MHz, OE = VIL See "Load conditions 2". - - - - - - - - 25 25 10 15 ns ns pF pF See "Load conditions 1". 5 50 50 - - - - - - - - - - 25 25 ns ns ns ns ns 1.0 to 2.0V 1.0 to 2.0V Condition min 25 10 10 50 20 20 - - 10 0 25 25 25 25 - typ - - - - - - - - - - - - - - - max - - - - - - 10 10 - - - - - - 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Load conditions 1
Load conditions 2
OUTPUT 40pF
OUTPUT
500 40pF 0V( t PHZ , t PZH ) 2.6V( t PLZ , t PZL )
SEIKO NPC CORPORATION --5
SM5837AF
t CR CLK
2.0V 1.0V
t CF 2.4V Min 1.5V 0.5V Max
t CH1 t CP1
t CL1
CLK t S1 DI0 - 11 t S1 DL0 - 10 t S1 RSTN t H1 t H1 t H1
1.5V
1.5V
1.5V
1.5V
CLK t PD t OH DO0 - 11 VALID VALID
1.5V
1.5V
t OEH OE t PZH t PHZ
t OEL 1.5V
0.5V
Hi-Z
1.5V t PZL t PLZ 1.5V
0.5V
DO0 - 11
Hi-Z
t CL2 SICK t S2 SDI
t CP2
t CH2 1.5V t H2 1.5V t CE t EC 1.5V
LEN
SEIKO NPC CORPORATION --6
SM5837AF
FUNCTIONAL DESCRIPTION
The SM5837AF provides a built-in 1H delay for video signal processing. The delay can be set to a length of 31 to 2078 clock delay bits. The delay length (LH) can be set using 2 methods, selected by the state of PARA. When PARA is HIGH, the delay length is set by parallel input data on DL0 to DL10. When PARA is LOW, the delay length is set by serial input data using SDI, SICK and LEN. Accordingly, the function of DL0/SDI, DL1/SICK and DL2/LEN is determined by PARA.
Parallel Input Set Method (PARA, DL0 to DL10)
When PARA is HIGH, parallel input data is used to set the delay length. The delay length (LH) is determined by the input data on DL0 to DL10 as shown in equation 1 and table 1.
LH = 31 + {DLk x 2 k }
k=0
10
(1)
Table 1. Delay bit length setting
DL10 0 0 0 0 0 0 0 0 0 1 1 1 1 DL9 0 0 0 0 0 0 0 1 1 1 1 1 1 DL8 0 0 0 0 0 1 1 1 1 1 1 1 1 DL7 0 0 0 0 0 1 1 1 1 1 1 1 1 DL6 0 0 0 0 0 1 1 1 1 1 1 1 1 DL5 0 0 0 0 0 1 1 1 1 1 1 1 1 DL4 0 0 0 0 0 0 0 0 0 0 0 1 1 DL3 0 0 0 0 0 0 0 0 0 0 0 1 1 DL2 0 0 0 0 1 0 0 0 0 0 0 1 1 DL1 0 0 1 1 0 0 1 0 1 0 1 1 1 DL0 0 1 0 1 0 1 0 1 0 1 0 0 1 Delay length 31 32 33 34 35 512 513 1024 1025 2048 2049 2077 2078
SEIKO NPC CORPORATION --7
SM5837AF
Serial Input Set Method (PARA, SDI, SICK, LEN)
When PARA goes LOW, 3-input serial data set method is used to set the delay length. Inputs DL3 to DL10 are ignored. SDI, SICK and LEN function as the serial data input, serial data shift clock and latch clock enable, respectively. The serial input data format, shown in figure XREF, comprises 11-bit serial data (S0 to S10) input on SDI in sync with SICK. The data on SDI is clocked into the serial-to-parallel converter shift register on the rising edge of SICK, and 11-bit parallel data is then latched into the delay length set register on the rising edge of LEN. The delay length (LH) is determined by the input data S0 to S10 (just as for parallel input data DL0 to DL10) as shown in equation 2. See also table 1. Note that SICK and CLK can be asynchronous.
LH = 31 + {Sk x 2 k }
k=0
10
(2)
SDI SICK LEN
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Dotted lines indicate possible SICK and LEN states.
Figure 1. Serial input data format
Delay Clock Input (CLK)
All 1H delay registers operate in sync with the delay clock CLK. The maximum clock frequency is 40MHz.
Input Data (DI0 to DI11)
DI0 to DI11 are the 12-bit data inputs.
Output Data (DO0 to DO11, OE)
DO0 to DO11 are the 12-bit data outputs. They are tristate outputs, with the output state selected by OE. When OE is HIGH, the outputs are enabled. When OE is LOW, the outputs are disabled (high-impedance state).
Reset (RSTN)
At power-ON, the internal timing generator circuits must be initialized by a LOW-level input on RSTN. After RSTN goes HIGH, the set delay length becomes active.
SEIKO NPC CORPORATION --8
SM5837AF
TIMING DIAGRAMS
Parallel Set Data (Delay Length = 31)
0 1 2 3 4 5 31 32 33 34 35
CLK RSTN DI0 - 11 OE DO0 - 11
UNKNOWN D1 D2 D3 Hi-Z D5 D1 D2 D3 D4 D5 D31 D32 D33 D34 D35
PARA=H, DL0-10=L
Serial Set Data (Delay Length = 32)
DL0/SDI
0 1 2 3 4 5 6 7 8 9 10
DL1/SICK DL2/LEN RSTN
1 2 3 32 33 34
CLK DI0 - 11 DO0 - 11
INVALID UNKNOWN D1 D2 D3 D1 D2 D3
PARA=L, DL3-10=Don't Care, OE=H
SEIKO NPC CORPORATION --9
SM5837AF
Please pay your attention to the following points at time of using the products shown in this document. The products shown in this document (hereinafter "Products") are not intended to be used for the apparatus that exerts harmful influence on human lives due to the defects, failure or malfunction of the Products. Customers are requested to obtain prior written agreement for such use from SEIKO NPC CORPORATION (hereinafter "NPC"). Customers shall be solely responsible for, and indemnify and hold NPC free and harmless from, any and all claims, damages, losses, expenses or lawsuits, due to such use without such agreement. NPC reserves the right to change the specifications of the Products in order to improve the characteristic or reliability thereof. NPC makes no claim or warranty that the contents described in this document dose not infringe any intellectual property right or other similar right owned by third parties. Therefore, NPC shall not be responsible for such problems, even if the use is in accordance with the descriptions provided in this document. Any descriptions including applications, circuits, and the parameters of the Products in this document are for reference to use the Products, and shall not be guaranteed free from defect, inapplicability to the design for the mass-production products without further testing or modification. Customers are requested not to export or re-export, directly or indirectly, the Products to any country or any entity not in compliance with or in violation of the national export administration laws, treaties, orders and regulations. Customers are requested appropriately take steps to obtain required permissions or approvals from appropriate government agencies.
SEIKO NPC CORPORATION
15-6, Nihombashi-kabutocho, Chuo-ku, Tokyo 103-0026, Japan Telephone: +81-3-6667-6601 Facsimile: +81-3-6667-6611 http://www.npc.co.jp/ Email: sales@npc.co.jp
NC9408BE 2006.04
SEIKO NPC CORPORATION --10

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